As transistors to 10nm, 7nm even develop smaller, the semiconductor industry is facing a real choice of material distress. Substrate, a channel, a gate and contact materials are urgently needed to assess. "In the 14nm, 10nm technology era, the architecture is determined." Intermolecular, Senior Vice President and General Manager of the semiconductor sector Raj Jammy said, using FinFET architecture "In most cases, of course, there are other options, such as fully depleted silicon on insulator (SOI). "For 10nm and 7nm speaking, Jammy considered high K metal gate will dominate, but the real challenge will be the channel itself. In the 10nm node, germanium (Ge) material is likely to be one channel. "But when you add germanium, there will be a series of problems." Jammy said. IMEC has recently made ​​some crucial breakthroughs in III-VFin FET (NFET) aspects. "Germanium has also been used." Steegen said, "In the process of the development of 10nm or 7nm pure germanium PFET is undoubtedly a valuable candidate materials." How 5nm technology node and beyond will develop is unclear, but Jammy has a practical approach. "If you drive the standard economic approach is applied to the node miniature, the first thing we found was a miniature goal is to add more functions on the chip." Jammy tell SEMI.